[aadl]: [aadl-modeling]: Modeling of ARINC653 multicore systems

[Pierre Dissaux]

Hi Julien,

I didn’t follow the discussions on that topic during the last meeting, but I well remember that the second option in your paper (System with Processors) was approved by the committee at the Winter 2014 meeting in Toulouse.

So, we do have a solution today to model multicore systems with or without virtual processors.
I will just comment the “Cons” you have identified for this current solution (§2.2 in your paper):

1. Do not capture the hardware nature of a core and potential interactions with buses. This might be critical
when analyzing the timing and shared resources of a core.

The core is represented by a processor. Why do you say it does not capture its hardware nature ?

2. Backwards compatibility of analysis tools (some analysis tools will not consider a system as a processor)

Which tool are you mentionning ?
We have no problem with that in AADL Inspector (Cheddar, Marzhin, ARINC 653 checker).
The changes we had to make one year ago to support systems as computing resources were very light.

Changing the components composition rules in the standard would have a much stronger impacts on both modelling and verification tools.

3. Compatibility of properties: properties using the processor as the OS needs to be updated. In that case, OSrelated
properties must also apply to system components then.

This has already been done for the Scheduling_Protocol
It is not a big issue to update a few property definitions if required

4. Lack of semantics: use the system as a container whereas a processor is a physical entity

This is a matter of point of view
A system can already have a Scheduling_Protocol, contain processors and virtual processors: it can actually be seen as a computing resource.
It also has all the required flexibility to incorporate complex architectures with buses and devices if necessary.

Moreover, the discussion we have today about processors could be extended to buses or devices. In all the cases, the system allows for a white box representation of complex hardware components.

Best regards

Pierre

From: Julien Delange 
Sent: Wednesday, April 01, 2015 8:39 PM
To: AADL Modeling ; sae-aadl-users at lists.sei.cmu.edu 
Subject: Re: [aadl-modeling]: Modeling of ARINC653 multicore systems

My apologies, please find the attachment.

 

Julien.

 

 

From: aadl-modeling-bounces+jdelange=sei.cmu.edu at lists.sei.cmu.edu [mailto:aadl-modeling-bounces+jdelange=sei.cmu.edu at lists.sei.cmu.edu] On Behalf Of Julien Delange
Sent: Wednesday, April 01, 2015 2:18 PM
To: sae-aadl-users at lists.sei.cmu.edu; AADL Modeling (aadl-modeling at lists.sei.cmu.edu)
Subject: [aadl-modeling]: Modeling of ARINC653 multicore systems

 

Dear all,

 

As discussed during the last meeting, please find a white paper that explains the modeling of multicore systems for ARINC653 architectures and motivates having processor subcomponents in process components types.

 

Julien.

 
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