[aadl-modeling]: Latency Analysis

[David K]

Hello,

I want to do a latency analysis and have a question about ports and
comonent-asccess again :/
I understand that port-connections are purely logical and
component-accesses are physical.
If I use a system-component to assemble my software-components and
subsystems how do I need to model the connections and especially the flows
(physically and logical)? I want to model the subcomponent communication
with port-connections and the communications between the systems with bus
accesses. My question is how do I get the data from the subcomponents of a
system e.g. "device1" to the subcomponents of the system "device3" with the
architecture of the image below.

Until now my models only contain port connections. So the subcomponents of
the systems are connected via ports. Then systems themselves are connected
via ports too because I don't know how to implement the data flows across
several systems with component-accesses.

As far as I tried I can't allocate multiple datatypes to one port interface
and I can't use the flow mechanism to connections. The examples I use for
my research doesn't contain such cases. They all use just one system with
it's subcomponents. Neither of them handles the communication between two
systems and their subcomponents via buses. For the FTA it was sufficient to
change the "bus accesses" from the image below into ports and then allocate
them to the bus. This works fine but I suppose this wasn't the correct way
to do it.


Thanks in advance
David

[image: image.png]
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