[aadl-modeling]: EMV2 Annex

Peter Feiler phf at sei.cmu.edu
Fri Jun 15 09:19:19 EDT 2018


Hi David,

Devices have logical interfaces (ports, data access) and physical interfaces (bus access).

You can associate error propagations with all these features.

EMV2 interprets all connections (port, data access, bus access) as propagation as well as along bindings – as stated in the EMV2 annex standard.

Fault tree analysis interprets all of these propagation path if they are present.

As you evolve your system you may first have a logical model and do the FTA only on port connections.
Then you may do a physical model and do an FTA on it.
Finally you add bindings  - in your case the binding of the connection between devices to the bus – the resulting FTA on it now shows the interactions between the logical and physical layers.

BTW you can use abstract components to model functional architectures.

Check out https://github.com/osate/examples/blob/master/SafetyTutorial/readme.md
The material is also in the OSATE help under Error Model Annex Documentation (aka Safety Analysis).

Peter

From: aadl-modeling-bounces+phf=sei.cmu.edu at lists.sei.cmu.edu [mailto:aadl-modeling-bounces+phf=sei.cmu.edu at lists.sei.cmu.edu] On Behalf Of David K
Sent: Thursday, June 14, 2018 10:22 AM
To: AADL Modeling <aadl-modeling at lists.sei.cmu.edu>
Subject: [aadl-modeling]: EMV2 Annex

Good afternoon,

I'm currently trying to model a "Fault Tree Analysis" which is working in it's basic functionality. Now I want to extend it. Before I' describe my problem some basic informations about my system. The image below shows a simplified version of my system. My issue is about modelling the individual communication between the hardware-systems. E.g. device1 has an specific error which only influences device2. device3 has the same error but is only influenced by device2. They all communicate over the bus "MVB1". Now my problem is how to model this case. I thought about modelling indivudal connections via port connections but they are used for software-components as far as I know. All resources I read about EMV2 modelling mainly use ports so it's hard for me to transfer this to bus accesses. I hope someone can give me some hints how to model this case.

Kind regards
David
[Unbenannt1.PNG]

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