[aadl]: [aadl-modeling]: Modeling page size

[Julien Delange]

Hi Stephane,

Thanks for your input. It seems that a Page_Size property would make sense. My question is more on what component it would be applicable? One can argue it should apply to the main memory but the page size of rather architecture- (meaning, processor) dependent. Other than say that this aspect is included in the hardware memory. We could then make it applicable to the processor, memory and system components.

We could then have something like
Page_Size: Size applies to (processor, system, memory);

Would that make sense?

Julien.



From: aadl-modeling-bounces+jdelange=sei.cmu.edu at lists.sei.cmu.edu [mailto:aadl-modeling-bounces+jdelange=sei.cmu.edu at lists.sei.cmu.edu] On Behalf Of Stéphane Rubini
Sent: Thursday, April 16, 2015 4:02 AM
To: aadl-modeling at lists.sei.cmu.edu
Subject: Re: [aadl-modeling]: Modeling page size

Dear Julien,
We have tried to model memory segmentation few years ago (article in AADL/UML workshop, 2011) in another
context of the ARINC systems.
As you, we propose to use  memory sub-components to represent the memory segment.
Hence, the property Memory_Size gives the segment size; the MMU implementation constraints this value
as a multiple of the page size. Another point is that some MMUs are able to manage different sizes of pages
(for instance 4K or 8K) following the operating system configuration.

I think that a memory component can represent an address space, that could be physical or virtual.
In the second case, the MMU work is hidden from the applicative software point of view,
and the constraints on the segment size is the result of this hidden work. So, a new
property Page_Size , if any, should be located within the memory component.

MMUs are also responsible of the definition of cacheable/non cacheable pages.
For this feature, a page_size property could have an interest: For instance
I imagine a shared data component with a non-cacheable status. One complete memory page
must be allocated in the address space for that data, if  other ones are cacheable "around".

Best,
Stéphane





Le mercredi 15 avril 2015 à 23:55 +0000, Julien Delange a écrit :
Dear all,



Follow-up on the previous discussion (modeling of a system tick). One constraint for deploying ARINC653 system is to define segments which size is a multiple of a page size. To define the memory segment, there is already the Memory_Size property. On the other hand, as far as I know, there is no property to capture the page size.

So, as for the tick property, I was wondering if somebody already tried to model such a characteristic and in that case,what property did they use? In case there is no existing property, what do you suggest? Also, the property should apply to a memory component (the hardware RAM component) or the processor (the OS that use the physical memory).



Any suggestion/comment appreciated!



Julien.




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